1. Field of the Invention
The present invention relates to a column decode circuit utilized for a random access memory, and more particularly relates to a column decode circuit comprised of MOSFETs (Metal-Oxide-Semi-conductor Field Effect Transistors) utilized for a static random access memory fabricated as a single chip integrated circuit preferably using MOSFETs.
A static random access memory is comprised of a large number of memory cells which are arranged in both column and row directions thereby forming a matrix of memory cells. When an address information is applied, one of the memory cells is accessed by means of both a column decode circuit and a row decode circuit. The row decode circuit specifies, by means of a row address decoder contained therein, a row address of the memory cells forming the matrix in accordance with a row address code of the address information. The column decode circuit specifies, by means of a column address decoder contained therein, a column address of the same memory cells forming the matrix in accordance with a column address code of the address information. Thus, an accessed one of the memory cells is accessed in accordance with the address information. The column decode circuit is divided into two major parts. One part is the column address decoder, and the other part is a transfer gate transistor. The column address decoder causes the transfer gate transistor to be conductive or nonconductive in accordance with the column address code of the address information. When the transfer gate transistor becomes conductive, the data output of the corresponding memory cell is provided from the random access memory by way of the transfer gate transistor and a conventional sense amplifier.
2. Description of the Prior Art
Three kinds of typical column decode circuits for a random access memory have been proposed in the prior art. The advantage of the first typical column decode circuit, as will be explained hereinafter, resides in that it has a high speed operating capability. However, the disadvantage of this column decode circuit is that it has a very high power consumption. The advantage of the second typical column decode circuit, as will be explained hereinafter, resides in that this column decode circuit has a very low power consumption. However, the disadvantage of this column decode circuit resides in that it has a low speed operating capability. The advantage of the third typical column decode circuit, as will be explained hereinafter, resides in that this column decode circuit has both a very low power consumption and a high speed operating capability; however, the third typical column decode circuit is disadvantageous in that this column decode circuit also requires a control circuit and a special control operation.